The signal transmission speed in optical transmission systems has been increasing year after year. In recent years, as a next-generation backbone network, the development and practical application of 40 Gbps optical transmission system have been carried on. However, the establishment of a new network other than an existing one requires a large amount of time and costs. Therefore, a configuration to connect an existing transmission system to a new high-speed system has been put into practice. In this case, a technique is required for multiplexing low-order group signals (signal with a low transmission rate) to generate a high-order group signal (signal with a high transmission rate). Meanwhile, the system for mapping a low-order group signal into a high-order group signal and the frame structure with each transmission rate are described in, for example, the ITU-T standard (G. 709).
FIG. 1 is a diagram illustrating an example of a system for multiplexing and transmitting a plurality of low-order group signals. Here, low-order group signals S1-Sn are supposed to be asynchronous to each other.
A multiplexing apparatus has plurality of buffer memories 1 for temporarily holding respective low-order group signals. A clock extraction circuit 2 extracts (or recovers) a clock signal from a corresponding low-order group signal. In FIG. 1, clocks CLK (W1)-CLK (Wn) are extracted from the low-order group signals S1-Sn, respectively. The extracted clocks CLK (W1)-CLK (Wn) are used as writing-in clocks for the buffer memories 1. In other words, data carried by the low-order group signals S1-Sn are written into corresponding buffer memories 1 using the clocks CLK (W1)-CLK (Wn), respectively.
Data held in respective buffer memories 1 are read out in synchronization with reading-out clocks CLK (R). The reading-out clock CLK (R) is synchronized with a clock used for the multiplexing process in a multiplexer 4. The multiplexer generates and transmits a high-order group signal by multiplexing the signals S1-Sn that carry corresponding data read out from respective buffer memories 1.
A phase comparison circuit 3 detects the phase error between a corresponding writing-in clock and the reading-out clock, and performs a stuffing process when the phase error deviates from a predetermined range. In the stuffing process, a redundant bit called a stuffing bit is inserted. At this time, stuffing information indicating that a stuffing bit has been inserted is written into a predetermined position in a corresponding low-order group signal frame.
The high-order group signal generated as described above is transmitted via a network. A reception apparatus 11 obtains the low-order group signals S1-Sn by demultiplexing the high-order group signal. At this time, upon detecting the stuffing information, the reception signal 11 removes the stuffing bit from a corresponding low-order group signal. The process of removing the stiffing bit in the reception apparatus is sometimes called destuffing.
The multiplex transmission system configured as explained above is described, for example, in Japanese Laid-open Patent Application No. 1-180142.
Meanwhile, in the multiplex transmission system configured as described above, a jitter is generated with the destuffing. The amount of the jitter depends on the frequency difference between the writing-in clock and the reading-out clock. However, generally, it is difficult to match the frequencies of clock signals that are generated independently from each other. In other words, usually, the frequencies of writing-in clocks CLK (W1)-CLK (Wn) do not perfectly match each other. For this reason, jitters generated with the low-order group signals S1-Sn are not the same as each other. Then, it has been difficult to appropriately or dynamically suppress such jitters.